NI AWR Design Environment
APLAC
Harmonic Balance/Transient Simulation
APLAC harmonic balance / transient circuit simulation engine is a key technology found within NI AWR Design Environment™. Acquired by AWR back in 2005, the APLAC simulation engine had been used in Nokia product development for many years as its foundry-approved harmonic balance method.
Today the APLAC harmonic balance simulation engine is further enhanced by the release of AWR’s patented Multi-Rate Harmonic Balance™ (MRHB) technology. MRHB enables users to simulate designs that were previously beyond the reach of the harmonic balance technique, and provides a 5x speed increase when simulating large, complex multi-tone designs.
The APLAC simulator offers multi-level analysis, including:
- DC operation point
- Linear frequency domain
- Time domain
- Multi-Rate Harmonic Balance
- Harmonic balance
- Phase noise
- Linear/non-linear noise including AC noise contributors, temperature
- Yield predictions and optimization
Learn more about APLAC capabilities by viewing videos on YouTube:
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