RFIC Design

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NI AWR Design Environment offers communication IC​ designers a platform to develop complete small-scale RFICs or RF front-ends for large-scale RFICs from system- to transistor-level design with native or 3rd party schematic/layout entry, fully integrated EM extraction for interconnects and on-chip passive components co-simulated with frequency (harmonic balance) and time (transient) domain circuit analysis. 


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Features

Design Entry  / Extraction / Simulation

  • Analog Office - Provides comprehensive simulation of RFIC technologies from system to final tape-out. RF/microwave-aware active and passive device models combine with Silicon foundry PDKs and Spectre netlist support to accurately capture the behavior of RF front-end blocks within an RFIC design. 
  • AXIEM and Analyst™ - 3D EM solvers provide S-parameter extraction of transmission lines, on-chip passives, ball-grid arrays, flip-chips, and wire bonds for post-layout verification.
  • NI AWR Design Environment - Integrates system-level analysis via Visual System Simulator™ (VSS) with Analog Office's harmonic balance, frequency- and time-domain analysis for RFICs. Define front-end architectures, budget RF blocks with simulation-ready behavioral models and simulate/optimize digitally modulated RF metrics such ACPR, EVM or BER.

Circuit / System / EM Simulation Products 

  • Analog Office - Circuit analysis with linear and nonlinear frequency and time-domain simulation
    • Design capture with industry-leading tuning
    • Linear and nonlinear frequency- and time-domain simulation​
      • APLAC RF harmonic balance for large-scale and highly nonlinear designs
    • HSPICE (and APLAC) simulation including transient/time-domain, AC and noise analysis extraction technology
    • ACE™ automated circuit extraction technology for interconnect modeling
    • OEA International NET-AN for 3D RLCK extraction​
  • Microwave Office - MMIC and RF PCB circuit analysis
    • Design capture with industry-leading tuning
    • Linear and nonlinear frequency- and time-domain simulation
      • APLAC harmonic balance for large-scale and highly nonlinear designs 
  • AXIEM and Analyst - 3D planar and 3D finite element method (FEM) EM​​ analysis for bumps, bond wires, ribbons
  • EM Socket -  Interoperability with ANSYS, CST, and Sonnet EM software products
  • Visual System Simulator - Communication systems, circuit-envelope analysis, and design partitioning/integration

Models and Libraries

Manufacturing and Test


Supported Technologies

  • LDMOS - Nonlinear models for high power transistors and RF ICs that simulate electrical phenomena and account for dynamic self-heating
  • SiGe - Delivers superior performance over standard silicon bipolar processes at a comparable cost level
  • CMOS SOI - Offers specific additional design advantages that include a significant reduction in cross-talk between RF and digital circuits on the same die and easy integration of high quality passive elements 
  • RF-CMOS - Analog Office offers select foundry PDKs for this low-cost, high-volume CMOS process technology developed for high-frequency electronics that support the integration of RF and baseband components onto a single chip

RFIC Design - Video Gallery