Employ Design-Flow Integration for Advanced Multichip RF Design

This article presents a modern design flow that translates the Cadence PDK into one that can be simulated in the NI AWR Design Environment platform to support chip-package co-design and EM verification. By importing the design into a dynamic library that can be used alongside the Cadence PDK, designers are able to effectively develop products based on disparate technologies using complex designs originally created in completely different environments. 
 
This article presents a modern design flow that translates the Cadence PDK into the NI AWR Design Environment platform to support chip-package co-design and EM verification.

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