Analog Office

RFIC/Analog IC Design

Analog Office software offers designers of RFICs and analog ICs an intuitive, flexible, and accurate design solution. Analog Office, along with Visual System Simulator™, AXIEM, and Analyst™ software tools form the NI AWR Design Environment platform. The unique architecture of the software streamlines designs and increases user productivity as it lets designers control and integrate best-in-class tools to capture, synthesize, simulate, optimize, lay out, extract, and verify RFIC and analog designs from the system level through to final tape-out.

Recent Additions

The latest release of NI AWR Design Environment platform, specifically the Analog Office software, provides for new and expanded capabilities.  Highlights include:

  • New Spectre Netlist Simulation Support - Enhanced support for Spectre netlist conversion and APLAC co-simulation for improved interoperability with Cadence, Synopsys and ADS allowing easier design re-use.
  • Enhanced Multi-Technology Projects - New design flow capabilities provides enhanced support for multi-technology projects, commonly used to simulate multi-chip modules that integrate diverse MMIC and RFIC devices on a single laminate package/module characterized with fully-integrated EM simulation. 
  • APLAC Additions - The transient assisted HB option (TAHB) used for digital divider circuits and accurate nonlinear phase noise measurements of analog and RF applications can now be more readily extended for use with oscillator analysis.

Learn more: What's New


  • Small-Scale CMOS and SiGe RFICs
  • RF Front-End Sections of Large-Scale RFICs
  • ​Multi-Chip Modules
  • Analog Circuits

Product Features


  • Schematic/Layout - Design entry with industry-leading tuning
  • APLAC - High-performance linear and nonlinear circuit simulation
    • Harmonic balance including transient-assisted HB, multi-rate HB, circuit envelope HB, as well as transient/time-domain
    • Transient/time-domain, AC and noise analysis
    • HSPICE co-simulation
    • Spectre netlist co-simulation support
  • Parasitic Extraction - Fully integrated planar and 3D EM with AXIEM and Analyst
    • Intelligent Net (iNet™) interconnect extraction technology
    • ACE™ automatic circuit extraction technology for interconnect modeling
    • OEA International NET-AN for 3D RLCK extraction
    • EM Socket™ interface for integration with third-party EM tools
  • DRC/LVS - Design rule checking/layout vs. schematic 
    • Support for tools such as Calibre, Assura and PowerDRC
  • PDKs - Process design kits (PDKs) from a wide range of Silicon foundries

​Supported Technologies

  • LDMOS - Nonlinear models for high power transistors and RF ICs 
  • SiGe - Delivers superior performance over standard silicon bipolar processes 
  • CMOS SOI - Reduced cross-talk between RF and digital circuits on the same die with easy integration of high quality passive elements 
  • RF CMOS - Select foundry PDKs for low-cost, high-volume CMOS process technologies